Applications Processor 361-Pin NFBGA T/R

The OMAP-L138 DSP+ARM processor is a low-power applications processor based on anARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than othermembers of the TMS320C6000 platform of DSPs.The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)to quickly bring to market devices with robust operating systems, rich user interfaces, and high processorperformance through the maximum flexibility of a fully integrated, mixed processor solution.The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions andprocesses 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor andmemory system can operate continuously.The ARM9 core has a coprocessor 15 (CP15), protection module, and data and program memorymanagement units (MMUs) with table look-aside buffers. The ARM9 core has separate 16-KB instructionand 16-KB data caches. Both are 4-way associative with virtual index virtual tag (VIVT). The ARM9 corealso has 8KB of RAM (Vector Table) and 64KB of ROM.The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a 32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. Thelevel 2 program cache (L2P) consists of a 256-KB memory space that is shared between program anddata space. L2 memory can be configured as mapped memory, cache, or combinations of the two.Although the DSP L2 is accessible by the ARM9 and other hosts in the system, an additional 128KB ofRAM shared memory is available for use by other hosts without affecting DSP performance.For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual propertyand prevents external entities from modifying user-developed algorithms. By starting from a hardwarebased“root-of-trust”, the secure boot flow ensures a known good starting point for code execution. Bydefault, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG portcan be enabled during the secure boot process during application development. The boot modules areencrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted andauthenticated when loaded during secure boot. Encryption and decryption protects the users’ IP and letsthem securely set up the system and begin device operation with known, trusted code.Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic SecureBoot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryptionscheme which not only protects the boot process but offers the ability to securely upgrade boot andapplication software code. A 128-bit device-specific cipher key, known only to the device and generatedusing a NIST-800-22 certified random number generator, is used to protect user encryption keys. Whenan update is needed, the customer uses the encryption keys to create a new encrypted image. Then thedevice can acquire the image through an external interface, such as Ethernet, and overwrite the existingcode. For more details on the supported security features or TI’s Basic Secure Boot, refer to theOMAP-L138 Processor Security User’s Guide (SPRUGQ9).

• Dual-Core SoC
  • 375- and 456-MHz ARM926EJ-S™ RISC MPU
  • 375- and 456-MHz C674x Fixed- and Floating- Point VLIW DSP
• ARM926EJ-S Core
  • 32- and 16-Bit ( Thumb®) Instructions
  • DSP Instruction Extensions
  • Single-Cycle MAC
  • ARM Jazelle® Technology
  • Embedded ICE-RT™ for Real-Time Debug
• ARM9™ Memory Architecture
  • 16KB of Instruction Cache
  • 16KB of Data Cache
  • 8KB of RAM (Vector Table)
  • 64KB of ROM
• C674x Instruction Set Features
  • Superset of the C67x+ and C64x+ ISAs
  • Up to 3648 MIPS and 2746 MFLOPS
  • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
  • 8-Bit Overflow Protection
  • Bit-Field Extract, Set, Clear
  • Normalization, Saturation, Bit-Counting
  • Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
  • 32KB of L1P Program RAM/Cache
  • 32KB of L1D Data RAM/Cache
  • 256KB of L2 Unified Mapped RAM/Cache
  • Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3):
  • 2 Channel Controllers
  • 3 Transfer Controllers
  • 64 Independent DMA Channels
  • 16 Quick DMA Channels
  • Programmable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core
  • Load-Store Architecture with Nonaligned Support
  • 64 General-Purpose Registers (32-Bit)
  • Six ALU (32- and 40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
• Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
  • Two Multiply Functional Units:
• Mixed-Precision IEEE Floating-Point Multiply Supported up to:
  • 2 SP x SP ? SP Per Clock
  • 2 SP x SP ? DP Every Two Clocks
  • 2 SP x DP ? DP Every Three Clocks
  • 2 DP x DP ? DP Every Four Clocks
• Fixed-Point Multiply Supports Two 32 x 32- Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Hardware Support for Modulo Loop Operation
  • Protected Mode Operation
  • Exceptions Support for Error Detection and Program Redirection
• Software Support
  • TI DSP BIOS™
  • Chip Support Library and DSP Library
• 128KB of RAM Shared Memory
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
• Two External Memory Interfaces:
  • EMIFA
• NOR (8- or 16-Bit-Wide Data)
• NAND (8- or 16-Bit-Wide Data)
• 16-Bit SDRAM with 128-MB Address Space
  • DDR2/Mobile DDR Memory Controller with one of the following:
• 16-Bit DDR2 SDRAM with 256-MB Address Space