Applications Processor 289-Pin BGA MICROSTAR

OMAP5912 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and reduced instruction set computer (RISC)technologies, incorporating a TMS320C55x DSP core and a high-performance ARM926EJ-S ARM® core.

Low-Power, High-Performance CMOS Technology

• 0.13-µm Technology
• 192-MHz Maximum Frequency
• 1.6 ± 5% V Core Voltage

ARM926EJ-S (MPU) Core

• Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
• 16K-Byte Instruction Cache
• 8K-Byte Data Cache
• Data and Program Memory Management Unit (MMU)
• 17-Word Write Buffer
• Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs

TMS320C55x (C55x) DSP Core

• One/Two Instructions Executed per Cycle
• Dual Multipliers (Two Multiply-Accumulates per Cycle)
• Two Arithmetic/Logic Units
• Five Internal Data/Operand Buses (3 Read Buses and 2 Write Buses)
• 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes)
• 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes)
• Instruction Cache (24K Bytes)
• Video Hardware Accelerators for DCT, iDCT, Pixel Interpolation, and Motion Estimation for Video Compression

250K Bytes of Shared Internal SRAM

Memory Traffic Controller (TC)

• 16-Bit EMIFS Supports up to 256M Bytes of External Memory (i.e., Async. ROM/RAM, NOR/NAND Flash, and Sync. Burst Flash)
• 16-Bit EMIFF to Access up to 64M Bytes of SDRAM, Mobile SDRAM, or Mobile DDR

DSP Memory Management Unit

DSP Peripherals

• Three 32-Bit Timers and Watchdog Timer
• Six-Channel DMA Controller
• Two Multichannel Buffered Serial Ports
• Two Multichannel Serial Interfaces

MPU Peripherals

• Three 32-Bit Timers and Watchdog Timer
• USB 1.1 Host and Client Controllers
• USB On-the-Go (OTG) Controller
• 3 USB Ports, One With an Integrated Transceiver
• Camera Interface for Parallel CMOS Sensors
• Real-Time Clock (RTC)
• Pulse-Width Tone (PWT) Interface
• Pulse-Width Light (PWL) Interface
• Keyboard Matrix Interface (6 x 5 or 8 x 8)
• HDQ/1-Wire Interface
• Multimedia Card (MMC) and Secure Digital (SD) Interface
• Up to 16 MPU General-Purpose I/Os
• Two LED Pulse Generators (LPGs)
• ETM9 Trace Module for ARM926EJ-S Debug
• 16-/18-Bit LCD Controller With Dedicated System DMA Channel
• 32-kHz Operating System (OS) Timer

Shared Peripherals

• 8 General-Purpose Timers
• Serial Port Interface (SPI)
• Three Universal Asynchronous Receiver/Transmitters (UARTs) (Two Supporting SIR mode for IrDA)
• Inter-Integrated Circuit (I²C) Master and Slave Interface
• Multimedia Card (MMC) and Secure Digital (SD) Interface
• Multichannel Buffered Serial Port
• Up to 64 Shared General-Purpose I/Os
• 32-kHz Synchro Counter

Endian Conversion Unit

Hardware Accelerators for Cryptographic Functions

• Random Number Generation
• DES and 3DES
• SHA-1 and MD5

Individual Power-Saving Modes for MPU/DSP/TC

On-Chip Scan-Based Emulation Logic

IEEE Std 1149.1 (JTAG) Boundary Scan Logic

Three 289-Ball BGA (Ball Grid Array) Packages (ZDY and ZZG - Lead-Free; GDY - With Lead)

The OMAP5912 device is targeted at the following applications:

• Applications Processing Devices
• Mobile Communications
  • WAN 802.11X
  • Bluetooth
  • GSM, GPRS, EDGE
  • CDMA
• Video and Image Processing
• Advanced Speech Applications
• Audio Processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and Other GSM Speech Codecs)
• Graphics and Video Acceleration
• Generalized Web Access
• Data Processing