ACLM2S010-1VFG256

Microsemi SmartFusion 2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM Cortex -M3 processor, and high-performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most reliable and highest security programmable logic solution. SmartFusion2 FPGAs offer up to 3.6X the gate density, up to 2X the performance of previous flash-based FPGA families, and includes multiple memory blocks and multiply accumulate blocks for DSP processing. The 166 MHz ARM Cortex-M3 processor is enhanced with an embedded trace macro cell (ETM), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals, including controller area network (CAN), Gigabit Ethernet, and high peed universal serial bus (USB). High speed serial interfaces include PCI EXPRESS (PCIe ), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) plus native serialization/deserialization (SERDES) communication, while DDR2/DDR3 memory controllers provide high speed memory interfaces.

• Single Event Upset (SEU) Immune
  • Zero FIT FPGA Configuration Cells
• Junction Temperature: 125°C - Military Temperature, 100°C - Industrial Temperature, 85°C - Commercial Temperature
• Single Error Correct Double Error Detect (SECDED) Protection on the Following:
  • Ethernet Buffers
  • CAN Message Buffers
  • Cortex-M3 Embedded Scratch Pad Memory (eSRAMs)
  • USB Buffers
  • PCIe Buffer
  • DDR Memory Controllers with Optional SECDED Modes
• Buffers Implemented with SEU Resistant Latches on the Following:
  • DDR Bridges (MSS, MDDR, FDDR)
  • Instruction Cache
  • MMUART FIFOs
  • SPI FIFOs
• NVM Integrity Check at Power-Up and On-Demand
• No External Configuration Memory Required-Instant On, Retains Configuration When Powered Off Security
• Design Security Features (Available on all Devices)
  • Intellectual Property (IP) Protection Through Unique Security Features and Use Models New to the PLD Industry
  • Encrypted User Key and Bit stream Loading, Enabling Programming in Less-Trusted Locations
  • Supply-Chain Assurance Device Certificate
  • Enhanced Anti-Tamper Features
  • Zeroization
• Data Security Features
  • Non-Deterministic Random Bit Generator (NRBG)
  • User Cryptographic Services (AES-256, SHA-256, Elliptical Curve Cryptographic (ECC) Engine)
  • User Physically Unclonable Function (PUF) Key Enrolment and Regeneration
  • CRI Pass-Through DPA Patent Portfolio License
  • Hardware Firewalls Protecting Microcontroller Subsystem (MSS) Memories Low Power
• Low Static and Dynamic Power
  • Flash*Freeze Mode for Fabric
• Power as low as 13 mW/Gbps per lane for SERDES devices
• Up to 50% lower total power than competing SoC devices High Performance FPGA
• Efficient 4-Input LUTs with Carry Chains for High Performance and Low Power
• Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large SRAM) with 400 MHz Synchronous Performance (512 x 36, 512 x 32, 1 kbit x 18, 1 kbit x 16, 2 kbit x 9, 2 kbit x 8, 4 kbit x 4, 8 kbit x 2, or 16 kbit x 1)
• Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2 Read Ports and 1 Write Port (micro SRAM)
• High-Performance DSP Signal Processing
  • Up to 240 Fast Math blocks with 18 x 18 Signed Multiplication, 17 x 17 Unsigned Multiplication and 44-Bit Accumulator