512K x 36 TeraSync FIFO, 2.5V

The IDT72T36135M is an exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memory with clocked read and write controls and a wide extended x36 bus to allow ample data flow. These FIFOs offer several key user benefits:. High density offering of 18 Mbit 200MHz R/W Clocks supporting 7.2Gbps of data throughput User selectable MARK location for retransmit User selectable I/O structure for HSTL or LVTTL Asynchronous/Synchronous translation on the read or write ports The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data at very high performance. The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW). The input port can be selected for either 2.5V LVTTL or HSTL operation, this operation is selected by the state of the WHSTL input during a master reset. A Write Chip Select input (WCS) is provided for use when the write port is in both LVTTL and HSTL modes. During operation the WCS input can be used to disable write port inputs (data only).

• Industry’s largest FIFO memory organization: IDT72T36135 - 524,288 x 36 - 18M-bits
• Up to 200 MHz Operation of Clocks
• Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync devices
• User selectable HSTL/LVTTL Input and/or Output
• User selectable Asynchronous read and/or write port timing
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input disables Write Port
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost Empty and Almost-Full flags
• Separate SCLK input for Serial programming of flag offsets
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty and Full flags signal FIFO status
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA) 50% more space saving than the leading 9M-bit FIFOs