512 x 36 SyncFIFO, 3.3V

The IDT72V3631 are designed to run off a 3.3V supply for exceptionally lowpower consumption. These devices are monolithic high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. The 512 x 36 dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO operates in First Word Fall Through mode and has flags to indicate empty and full conditions and conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. Communication between each port may take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices may be used in parallel to create wider data paths. Expansion is also possible in word depth. These devices are a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOWto-HIGH transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous control. The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are two-stage synchronized to CLKA. The Output Ready (OR) flag and Almost-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be programmed from port A or through a serial input. The IDT72V3641 are characterized for operation from 0°C to 70°C. These devices are fabricated using high speed, submicron CMOS technology.

• Storage capacity: IDT72V3631 - 512 x 36
• Supports clock frequencies up to 67 MHz
• Fast access times of 10ns
• Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge)
• Clocked FIFO buffering data from Port A to Port B
• Synchronous read retransmit capability
• Mailbox register in each direction
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• Input Ready (IR) and Almost-Full (AF) flags synchronized by CLKA
• Output Ready (OR) and Almost-Empty (AE) flags synchronized by CLKB
• Available in space-saving 120-pin thin quad flat package (TQFP)
• Easily expandable in width and depth