4Q x36 2M Multi-Queue, 3.3V

The IDT72V51256 multi-queue flow-control devices are single chip within which anywhere between 1 and 4 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 166MHz, with access times of 3.7ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. The device provides Full flag and Output Valid flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 4 bit programmable flag busses are available, providing status of all queues, including queues not selected for write or read operations, these flag busses provide an individual flag per queue. Bus Matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner. A packet mode of operation is also provided when the device is configured for 36 bit input and 36 bit output port sizes. The Packet mode provides the user with a flag output indicating when at least one (or more) packets of data within a queue is available for reading. The Packet Ready provides the user with a means by which to mark the start and end of packets of data being passed through the queues. The multi-queue device then provides the user with an internally generated packet ready status per queue.

• Memory density: IDT72V51256 - Total Available Memory = 2,359,296 bits
• Configurable from 1 to 4 Queues
• Queues may be configured at master reset from the pool of Total Available Memory in blocks of 256 x 36
• Independent Read and Write access per queue
• User programmable via serial port
• 100% Bus Utilization, Read and Write on every clock cycle
• 166 MHz High speed operation (6ns cycle time)
• 3.7ns access time
• Individual, Active queue flags (OV, FF, PAE, PAF, PR)
• 4 bit parallel flag status on both read and write ports
• Provides continuous PAE and PAF status of up to 4 Queues
• Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width)
• FWFT mode of operation on read port
• Packet mode operation
• Partial Reset, clears data in single Queue
• Expansion of up to 8 multi-queue devices in parallel is available
• JTAG Functionality (Boundary Scan)
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available