3.3V CMOS 20-Bit Buffer with 5.0V Tolerant I/O

This 20-bit buffer is built using advanced dual metal CMOS technology. The LVC16827A provides high-performance bus interface buffering for wide data/address paths or buses carrying parity. Two pairs of NAND-ed output enable controls offer maximum control flexibility and are organized to operate the device as two 10-bit buffers or one 20-bit buffer. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The LVC16827A buffer is ideally suited for driving high capacitance loads and low impedance backplanes. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. The LVC16827A has been designed with a ±24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance.

• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in TSSOP package