32-BIT W/ CACHE

Leveraging many of the same performance enhancements used by RISC designs as well as providing innovative architectural techniques, the MC68060 harnesses new levels of performance for the M68000 family. Incorporating 2.5 million transistors on a single piece of silicon, the MC68060 employs a deep pipeline, dual issue superscalar execution, a branch cache, a high-performance floating-point unit (MC68060 only), eight Kbytes each of on-chip instruction and data caches, and dual on-chip demand paging MMUs (MC68060 and MC68LC060 only). The MC68060 allows simultaneous execution of two integer instructions (or an integer and a floating-point instruction) and one branch instruction during each clock. The MC68060 features a full internal Harvard architecture. The instruction and data caches are designed to support concurrent instruction fetch, operand read, and operand write references on every clock. Separate 8- Kbyte instruction and 8-Kbyte data caches can be frozen to prevent allocation over time-critical code or data. The independent nature of the caches allows instruction stream fetches, data-stream fetches, and external accesses to occur simultaneously with instruction execution. The operand data cache is four-way banked to permit simultaneous read and write access each clock. A very high bandwidth internal memory system coupled with the compact nature of the M68000 family code allows the MC68060 to achieve extremely high levels of performance, even when operating from low-cost memory such as a 32-bit wide dynamic random access memory system. Instructions are fetched from the internal cache or external memory by a four-stage instruction fetch pipeline. The MC68060 variable-length instruction system is internally decoded into a fixed-length representation and channeled into an instruction buffer. The instruction buffer acts as a FIFO which provides a decoupling mechanism between the instruction fetch unit and the operand execution units. Fixed format instructions are dispatched to dual four-stage pipelined RISC operand execution engines where they are then executed. The branch cache also plays a major role in achieving the high performance levels of the MC68060. It has been implemented such that most branches are executed in zero cycles. Using a technique known as branch folding, the branch cache allows the instruction fetch pipeline to detect and change the instruction prefetch stream before the change of flow affects the instruction execution engines, minimizing the need for pipeline refill. In addition to substantial cost and performance benefits, the MC68060 also offers advantages in power consumption and power management. The MC68060 automatically minimizes power dissipation by using a fully-static design, dynamic power management, and low-voltage operation. It automatically powers-down internal functional blocks that are not needed on a clock-by-clock basis. Explicitly, the MC68060 power consumption can be controlled from the operating system. Although the MC68060 operates at a lower operating voltage, it directly interfaces to both 3-V and 5-V peripherals and logic. Complete code compatibility with the M68000 family allows the designer to draw on existing code and past experience to bring products to market quickly. There is also a broad base of established development tools, including real-time kernels, operating systems, languages, and applications, to assist in product design. The functionality provided by the MC68060 makes it the ideal choice for a range of high-performance embedded applications and computing applications. With M68000 family code compatibility, the MC68060 provides a range of upgrade opportunities to virtually any existing MC68040 application.

• Fully User-Code Compatible with MC68040
• Superscalar Implementation of M68000 Architecture
  • Dual Integer Instruction Execution Improves Performance
• Branch Cache Reduces Branches to Zero Cycles
• Executes Three Instructions per Clock
• Dual 8-Kbyte On-Chip Caches
  • Separate Data and Instruction Caches
  • Simultaneous Access
  • Data Cache is Four-Way Banked to Allow Read and Write Access on Each Clock
• Bus Snooping
• Independent Instruction and Data Paged MMUs (MC68060 and MC68LC060 Only)
• Full 32-Bit Nonmultiplexed Address and Data Bus
  • Optimized to Achieve Very High Performance Using 32-Bit Memory System
  • Can Operate Bus at 1/2-or 1/4-Speed of Internal Clock
  • 32-Bit Bus Maximizes Data Throughput
  • Nonmultiplexed Bus Simplifies Design
  • Four-Deep Store Buffer and One-Deep Push Buffer to Maximize Write Bandwidth
  • MC68040-Compatible Bus Provides Simple Hardware Migration Path
• Power Management
  • Automatic Power-Down of Unused Blocks of Logic on a Clock-by-Clock Basis
  • Low-Voltage Operation at 3.3 V, with 3.3-V and 5-V I/O Capability
  • LPSTOP Mode Provides an Idle State for Lowest Standby Current
  • Static CMOS Technology Reduces Power in Normal Operation
• IEEE-Compatible On-Chip FPU (MC68060 Only)
• Available in 40-MHz (MC68EC060 only), 50-MHz, and 66-MHz Speeds
• Packaging
  • Ceramic Pin Grid Array (PGA)
  • Ceramic Quad Flat Pack (CQFP)