28-Bit Configurable Registered Buffer for DDR2

This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The ICSSSTUAF32865A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. The ICSSSTUAF32865A includes a parity checking function. The ICSSSTUAF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW).

• 28-bit 1:2 registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on CSGateEN and RESET inputs
• Low voltage operation: VDD = 1.7V to 1.9V
• Available in 160-ball LFBGA package