25-Bit Configurable Registered Buffer for DDR2

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUB32866B operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).

• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
• Supports SSTL_18 JEDEC specification on data inputs and outputs
• Supports LVCMOS switching levels on CSR and RESET inputs
• Low voltage operation VDD = 1.7V to 1.9V
• Available in 96 BGA package
• Drop-in replacement for ICSSSTUA32864
• Green packages available