2:4,LVPECL Output Fanout Buffer

The 8SLVP1204 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1204 is characterized to operate from a 3.3V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1204 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

• Four low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential PCLKx pairs can accept the following differential input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input, (input select)
• Output skew: 5ps (typical), at 3.63V
• Propagation delay: 200ps (typical), at 3.63V
• Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature