2-output 1.5 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

The 9DBU0231 is a member of IDT’s 1.5 V Ultra-Low-Power (ULP) PCIe family. The device has 2 output enables for clock management.

• LP-HCSL outputs; save 8 resistors compared to standard HCSL outputs
• 45 mW typical power consumption in PLL mode; minimal power consumption
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by common clock sources
• LP-HCSL differential clock outputs; reduced power and board space
• Programmable slew rate for each output; allows tuning for various line lengths
• Programmable output amplitude; allows tuning for various application environments
• Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Configuration can be accomplished with strapping pins; SMBus interface not required for device control
• 3.3 V tolerant SMBus interface works with legacy controllers
• Space-saving 4x4 mm 24-pin VFQFPN; minimal board space