1K x 36 SyncFIFO, 5.0V

The IDT723643 are monolithic, high-speed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memories which support clock frequencies up to 83 MHz and have read access times as fast as 8 ns. The 1,024 x 36 dual-port SRAM FIFO buffers data from port A to port B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations. These devices are synchronous (clocked) FIFOs, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFO via two mailbox registers. The mailbox registers" width matches the selected Port B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on these FIFOs: Reset and Partial Reset. Reset initializes the read and write pointers to the first location of the memory array and selects serial flag programming, parallel flag programming, or one of three possible default flag offset settings, 8, 16 or 64. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Reset, any settings existing prior to Partial Reset are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings.

• Memory storage capacity:
  • IDT723643 - 1,024 x 36
• Clocked FIFO buffering data from Port A to Port B
• Clock frequencies up to 83 MHz (8 ns access time)
• IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte)
• Big- or Little-Endian format for word and byte bus sizes
• Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)
• Easily expandable in width and depth
• Auto power down minimizes power dissipation
• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)