1K x 18 DualSync FIFO, 5.0V

The IDT72825LB are dual 18-bit-wide synchronous (clocked) First-in, First-out (FIFO) memories. One dual IDT72825LB device is functionally equivalent to two IDT72225LB FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs contained in these devices has an 18-bit input and output port. Each input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port of each FIFO bank is controlled by another clock pin (RCLK) and another enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port of each FIFO for three-state control of the output. The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available for each FIFO that is implemented as a single device configuration. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard Mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word.

• Offers optimal combination of large capacity (8K), high speed, design flexibility, and small footprint
• Ideal for the following applications:
  • Network switching
  • Two level prioritization of parallel data
  • Bidirectional data transfer
  • Bus-matching between 18-bit and 36-bit data paths
  • Width expansion to 36-bit per package
  • Depth expansion to 8,192 words per package
• 10ns read/write cycle time, 6.5ns access time
• IDT Standard or First Word Fall Through timing
• Single or double register-buffered Empty and Full Flags
• Easily expandable in depth and width
• Asynchronous or coincident Read and Write clocks
• Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings
• Half-Full flag capability
• Output Enable puts output data bus in high-impedance state
• High-performance submicron CMOS technology
• Available in the 128-pin Thin Quad Flatpack (TQFP). Also available for the IDT72825LB, in the 121-lead, 16 x 16 mm plastic Ball Grid Array (PBGA)
• Industrial temperature range (-40°C to +85°C) is available