1:4, Differential-to-LVCMOS / LVTTL Zero Delay Clock Generator

The ICS87004I is a highly versatile 1:4 Differentialto-LVCMOS/LVTTLClock Generator. The ICS87004Ihas two selectable clock inputs. The CLK0, nCLK0and CLK1, nCLK1 pairs can accept most standarddifferential input levels. Internal bias on the nCLK0 andnCLK1 inputs allows the CLK0 and CLK1 inputs to acceptLVCMOS/LVTTL. The ICS87004I has a fully integrated PLL and canbe configured as a zero delay buffer, multiplier or divider and has aninput and output frequency range of 15.625MHz to 250MHz. Thereference divider, feedback divider and output divider are eachprogrammable, thereby allowing for the following output-to-inputfrequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The externalfeedback allows the device to achieve “zero delay” between the inputclock and the output clocks. The PLL_SEL pin can be used tobypass the PLL for system test and debug purposes. In bypassmode, the reference clock is routed around the PLL and into theinternal output dividers.

• Four LVCMOS/LVTTL outputs, 7? typical output impedance
• Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
• CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration with configurable frequencies
• Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 65ps (maximum)
• Static phase offset: 50ps ± 150ps (3.3V ± 5%), CLK0/nCLK0
• Full 3.3V or 2.5V output operating supply
• 5V tolerant
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages