÷1/÷2 Differential-to-LVDS Clock Generator

The 87421I is a high performance ÷1/÷2 Differential-to-LVDS Clock Generator. The CLK, nCLK pair can accept most standard differential input levels. The 87421I is characterized to operate from a 3.3V power supply. Guaranteed part-to-part skew characteristics make the 87421I ideal for those clock distribution applications demanding well defi ned performance and repeatability.

• One differential LVDS output
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS levels with resistor bias on nCLK input
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.7ns (maximum)
• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package