EEPROM Programmable Clock Generator

The IDT5V49EE501 is a programmable clock generatorintended for high performance data-communications,telecommunications, consumer, and networkingapplications. There are four internal PLLs, each individuallyprogrammable, allowing for four unique non-integer-relatedfrequencies. The frequencies are generated from a singlereference clock. The reference clock can come from one ofthe two redundant clock inputs. Automatic or manualswitchover function allows any one of the redundant clocksto be selected during normal operation. The IDT5V49EE501 is in-system, programmable and canbe programmed through the use of I2C interface. Aninternal EEPROM allows the user to save and restore theconfiguration of the device without having to reprogram it onpower-up. Each of the four PLLs has an 7-bit reference divider and a12-bit feedback divider. This allows the user to generatefour unique non-integer-related frequencies. The PLL loopbandwidth is programmable to allow the user to tailor thePLL response to the application. For instance, the user cantune the PLL parameters to minimize jitter generation or tomaximize jitter attenuation. Spread spectrum generationand/or fractional divides are allowed on two of the PLLs. There are a total of four 8-bit output dividers. Each outputbank can be configured to support LVTTL, LVPECL, LVDSor HCSL logic levels. Out0 (Output 0) supports 3.3V singleended output only. The outputs are connected to the PLLsvia a switch matrix. The switch matrix allows the user toroute the PLL outputs to any output bank. This feature canbe used to simplify and optimize the board layout. Inaddition, each output"s slew rate and enable/disablefunction is programmable.

• Four internal PLLs
• Internal non-volatile EEPROM
• Fast (400kHz) mode I2C serial interface
• Input frequency range: 1 MHz to 200 MHz
• Output frequency range: 4.9 kHz to 500 MHz
• Reference crystal input with programmable linear load capacitance
  • Crystal frequency range: 8 MHz to 50 MHz
• Each PLL has a 7-bit reference divider and a 12-bit feedback-divider
• 8-bit output-divider blocks
• Fractional division capability on one PLL
• Two of the PLLs support spread spectrum generation capability
• I/O Standards:
  • Outputs - 3.3 V LVTTL/ LVCMOS
  • Outputs - LVPECL, LVDS and HCSL
  • Inputs - 3.3 V LVTTL/ LVCMOS
• Programmable slew rate control
• Programmable loop bandwidth
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with auto and manual switchover options
• Individual output enable/disable
• Power-down mode
• 3.3V core VDD
• Available in VFQFPN package
• -40 to +85 C Industrial Temp operation