Counter/Divider Dual 4-Bit Binary UP 14-Pin SOIC T/R

The ’HC393 devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK) input. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The ’HC393 devices have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.

Wide Operating Voltage Range of 2 V to 6 V

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 80-µA Max I_CC

Typical t_pd = 13 ns

±4-mA Output Drive at 5 V

Low Input Current of 1 µA Max

Dual 4-Bit Binary Counters With Individual Clocks

Direct Clear for Each 4-Bit Counter

Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent