Zero Delay PLL Clock Buffer Single 16-Pin TSSOP

The CY23FS04 is a FailSafe zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO. This serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS04 is that the DCXO is the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal that is connected to the DCXO must be an integer factor of the frequency of the reference clock. This factor is set by two select lines: S[2:1]. The output power supply VDD can be connected to either 2.5 V or 3.3 V. VDDC is the power supply pin for internal circuits and must be connected to 3.3 V.

• Internal digital controlled crystal oscillator (DCXO) for continuous glitch-free operation
• Zero input-output propagation delay
• Low jitter (35 ps max RMS) outputs
• Low output-to-output skew (200 ps max)
• 4.17 MHz to 166.7 MHz reference input
• Supports industry standard input crystals
• 166.7 MHz outputs
• 5 V tolerant Inputs
• Phase-locked loop (PLL) bypass mode
• Dual reference inputs
• 16-Pin thin shrunk small outline package (TSSOP)
• 2.5 V or 3.3 V output power supplies
• 3.3 V core power supply
• Industrial temperature range