SMARTFUSION

The SmartFusion family of cSoCs builds on the technology first introduced with the Fusion mixed signal FPGAs. SmartFusion cSoCs are made possible by integrating FPGA technology with programmable high-performance analog and hardened ARM Cortex-M3 microcontroller blocks on a flash semiconductor process. The SmartFusion cSoC takes its name from the fact that these three discrete technologies are integrated on a single chip, enabling the lowest cost of ownership and smallest footprint solution to you.

• Microcontroller Subsystem (MSS)
• Hard 100 MHz 32-Bit ARM® Cortex™-M3
  • 1.25 DMIPS/MHz Throughput from Zero Wait State Memory
  • Memory Protection Unit (MPU)
  • Single Cycle Multiplication, Hardware Divide
  • JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 wires), and Single Wire Viewer (SWV) Interfaces
• High-Performance FPGA
• Based on proven ProASIC®3 FPGA Fabric
• Low Power, Firm-Error Immune 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Nonvolatile, Instant On, Retains Program When Powered Off
• 350 MHz System Performance
• Programmable Analog Analog Front-End (AFE)
• Up to Three 12-Bit SAR ADCs
  • 500 Ksps in 12-Bit Mode
  • 550 Ksps in 10-Bit Mode
  • 600 Ksps in 8-Bit Mode
• Analog Compute Engine (ACE)
• Offloads Cortex-M3–Based MSS from Analog Initialization and Processing of ADC, DAC, and SCBs
• Sample Sequence Engine for ADC and DAC Parameter Set-Up
• Post-Processing Engine for Functions such as LowPass Filtering and Linear Transformation
• Easily Configured via GUI in Libero® System-on-Chip (SoC) Software