Bus Controller, DMA Backend Interface To External Memory

The Core1553BBC provides a complete, MIL-STD-1553B Bus Controller (BC). A typical system implementation using the Core1553BBC. Core1553BBC reads message descriptor blocks from the memory and generates messages that are transmitted on the 1553B bus. Data words are read from the memory and transmitted on the 1553B bus. Data received is written to the memory. The core can be configured directly to connect to synchronous or asynchronous memory devices. The core consists of five main blocks: the 1553B encoder, the 1553B decoder, a protocol controller block, a CPU interface, and a backend interface. A single 1553B encoder takes each word to be transmitted and serializes it using Manchester encoding. The encoder includes independent logic to prevent the BC from transmitting for greater than the allowed period and to provide loopback fail logic. The loopback logic monitors the received data and verifies that the core has correctly received every word that is transmitted. The encoder output is gated with the bus enable signals to select which buses the RT should be transmitting. Since the BC knows which bus is in use at any time, only a single decoder is required. The decoder takes the serial Manchester received data from the bus and extracts the received data words. The decoder requires a 12, 16, 20, or 24 MHz clock to extract the data and the clock from the serial stream. The decoder contains a digital phased lock loop (PLL) that generates a recovery clock used to sample the incoming serial data. The data is then deserialized and the 16-bit word decoded. The decoder detects whether a command, status or data word has been received and checks that no Manchester encoding or parity errors occurred in the word.

• Supports MIL-STD-1553B
• Interfaces to External RAM
  • Supports up to 128kbytes of Memory
  • Synchronous or Asynchronous Backend Interface
  • Backend Interface Identical to Core1553BRT
• Selectable Clock Rate of 12, 16, 20, or 24 MHz
  • Provides Direct CPU Access to Memory
• Interfaces to Standard 1553B Transceivers
• Fully Automated Message Scheduling
  • Frame Support
  • Conditional Branching and Sub-routines
  • Variable Inter-message Gaps and RT Response Times
  • Real Time Clock for Message Scheduling
  • Asynchronous Message Support
  • Synthesis Scripts
• Actel-Developed Testbenches, VHDL and Verilog