Media Processor

TMS320DM8127 DaVinci Digital Media processors are highly integrated,programmable platforms that leverage the technology to meet the processing needsof the following applications to name a few:IP Network Cameras IndustrialAutomation Network Cameras Stereo Cameras Video Surveillance HD VideoConferencing Car Black BoxHome Audio and Video Equipment The device enables Original-Equipment Manufacturers (OEMs) andOriginal-Design Manufacturers (ODMs) to quickly bring to market devicesfeaturing robust operating systems support, rich user interfaces, and highprocessing performance through the maximum flexibility of a fully integratedmixed processor solution. The device also combines programmable video and audioprocessing with a highly integrated peripheral set. Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension,TI C674x VLIW floating-point DSP core, and high-definition video and imagingcoprocessors. The ARM lets developers keep control functions separate from A/Valgorithms programmed on the DSP and coprocessors, thus reducing the complexityof the system software. The ARM Cortex-A8 32-Bit RISC Core with Neonfloating-point extension includes: 32KB of Instruction cache; 32KB of Datacache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM. The rich peripheral set provides the ability to control external peripheraldevices and communicate with external processors. For details on each of theperipherals, see the related sections in this document and the associatedperipheral reference guides. The peripheral set includes: HD Video ProcessingSubsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch]with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping,AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIex1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DITmode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSPmultichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPIserial interfacesThree MMC/SD/SDIO serial interfacesFour I2C masterand slave interfaces Parallel Camera Interface (CAM)Up to128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers Systemwatchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bitasynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpinLockMailbox The TMS320DM8127 DaVinci Digital Media processors also include ahigh-definition video and imaging coprocessor 2 (HDVICP2) to off-load many videoand imaging processing tasks from the DSP core, making more DSP MIPS availablefor common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinciDigital Media processors have a complete set of development tools for both theARM and DSP which include C compilers, a DSP assembly optimizer to simplifyprogramming and scheduling, and a Microsoft® Windows debugger interface forvisibility into source code execution. The C674x DSP core is the high-performance floating-point DSP generation inthe TMS320C6000 DSP platform and is code-compatible with previous generationC64x Fixed-Point and C67x Floating-Point DSP generation. The C674xFloating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB ofL1 data memory. Up to 32KB of L1P can be configured as program cache. Theremaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1Dcan be configured as data cache. The remaining memory is noncacheableno-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can bedefined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip

High-Performance DaVinci Video Processors

• Up to 1-GHz ARM Cortex-A8 RISC Core
• Up to 750-MHz C674x VLIW DSP
• Up to 6000 MIPS and 4500 MFLOPS
• Fully Software-Compatible with C67x+, C64x+

ARM Cortex-A8 Core

• ARMv7 Architecture
  • In-Order, Dual-Issue, Superscalar Processor Core
  • Neon Multimedia Architecture
  • Supports Integer and Floating Point
  • Jazelle RCT Execution Environment

ARM Cortex-A8 Memory Architecture

• 32KB of Instruction and Data Caches
• 256KB of L2 Cache
• 64KB of RAM, 48KB of Boot ROM

TMS320C674x Floating-Point VLIW DSP

• 64 General-Purpose Registers (32-Bit)
• Six ALU (32-/40-Bit) Functional Units
  • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP(IEEE Double Precision/64-Bit) Floating Point
  • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
  • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
• Two Multiply Functional Units
  • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
    • 2 SP x SP - SP Per Clock
    • 2 SP x SP - DP Every Two Clocks
    • 2 SP x DP - DP Every Three Clocks
    • 2 DP x DP - DP Every Four Clocks
  • Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-BitMultiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle

128KB of On-Chip Memory Controller RAM

Imaging Subsystem

• Camera Sensor Connection
  • Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8-and 16-Bit)
  • CSI2 Serial Connection
• Image Sensor Interface for Handling Image and Video Data From the Camera Sensor
• Image Pipe Interface for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM
• Image Pipe for Real-Time Image and Video Processing
• Resizer
  • Resizing Image and Video From 1/16x to 8x
  • Generating Two Different Resizing Outputs Concurrently
• Hardware 3A Engine for Generating Key Statistics for 3A (AE, AWB, and AF) Control

Face Detect Engine

• Hardware Face Detection for up to 35 Faces at OPP100

Programmable High-Definition Video Image Coprocessing Engine

• Encode, Decode, Transcode Operations
• H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG

Media Controller

• Controls the HDVPSS and ISS

Endianness

• ARM and DSP Instructions/Data - Little Endian

HD Video Processing Subsystem

• One 165-MHz HD Video Capture Input
  • One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports
• Two 165-MHz HD Video Display Outputs
  • One 16-, 24-, or 30-Bit Output and One 16- or 24-BitOutput
• Composite or S-Video Analog Output
• Macrovision Support Available
• Digital HDMI 1.3 Transmitter With Integrated PHY
• Advanced Video Processing Features Such as Scan, Format, Rate Conversion
• Three Graphics Layers and Compositors

Dual 32-Bit DDR2/DDR3 SDRAM Interfaces

• Supports up to DDR2-800 and DDR3-1066
• Up to Eight x 8 Devices Total 2GB of Total Address Space
• Dynamic Memory Manager
  • Programmable Multi-Zone Memory Mapping and Interleaving
  • Enables Efficient 2D Block Accesses
  • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
  • Optimizes Interlaced Accesses