64K/1K FL 12 CLK ISP/IAP COMM

The P89C51RD2 nxp contains a non-volatile 8KB/16KB/32KB/64KB Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application. In-Application Programming (IAP) means that the microcontroller fetches new program code and reprograms itself while in the system. This allows for remote programming over a modem link. A default serial loader (boot loader) program in ROM allows serial In-System programming of the Flash memory via the UART without the need for a loader in the Flash code. For In-Application Programming, the user program erases and reprograms the Flash memory by use of standard routines contained in ROM. The device supports 6-clock/12-clock mode selection by programming a Flash bit using parallel programming or In-System Programming. In addition, an SFR bit (X2) in the clock control register (CKCON) also selects between 6-clock/12-clock mode. Additionally, when in 6-clock mode, peripherals may use either 6 clocks per machine cycle or 12 clocks per machine cycle. This choice is available individually for each peripheral and is selected by bits in the CKCON register. This device is a Single-Chip 8-Bit Microcontroller manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The instruction set is 100% compatible with the 80C51 instruction set. The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C51RD2 nxp make it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control.

• 80C51 Central Processing Unit
• On-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability
• Boot ROM contains low level Flash programming routines for downloading via the UART
• Can be programmed by the end-user application (IAP)
• Parallel programming with 87C51 compatible hardware interface to programmer
• Supports 6-clock/12-clock mode via parallel programmer (default clock mode after ChipErase is 12-clock)
• 6-clock/12-clock mode Flash bit erasable and programmable via ISP
• 6-clock/12-clock mode programmable “on-the-fly” by SFR bit
• Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the CPU is in 6-clock mode
• Speed up to 20 MHz with 6-clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle
• Fully static operation
• RAM expandable externally to 64 kbytes
• Four interrupt priority levels
• Seven interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART
  • Framing error detection
  • Automatic address recognition
• Power control modes
  • Clock can be stopped and resumed
  • Idle mode
  • Power down mode
• Programmable clock-out pin
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Programmable Counter Array (PCA)
  • PWM
  • Capture/compare