32 bit, single processor core with sensor subsystem, Pentium ISA compatible Quark microcontroller

32 bit, single processor core with sensor subsystem, Pentium ISA compatible Quark microcontroller CPU
32-bit processor @ 32 MHz Intel® Pentium® x86-compatible without
x87 floating point unit
8 KB instruction cache, 2-way associative

Sensor subsystem
32-bit DSP core @ 32 MHz
Supporting ARCv2 ISA and floating
point unit
8 KB instruction cache, 2-way associative
8 KB DCCM

Pattern-matching
accelerator
Hardware pattern recognition IP
128 neurons with 128 components
per neuron

Flash
384 KB on-die flash
192 KB dedicated to host processor
192 KB dedicated to sensor system
8 KB OTP

RAM
80 KB on-die SRAM

General-use timers
4

Watchdog timer
1

Real-time clock
Sources a 32-bit counter running from
1 Hz up to 32.768 KHz

UARTs
2 16550-compliant interfaces
Baud rates from 300 to 2M

SPI
2 masters with up to 4 devices
per master
1 slave

General purpose I/O
32 independently configurable
16 additional available via sensor subsystem

USB controller
1.1 device-only controller

I2C
2 general-purpose I2C interfaces, configurable either as master or slave
2 master-only interfaces available in the sensor subsystem
Interface speeds: 100 kbps, 400 kbps, and 1 Mbps

I2S
2 I2S interfaces:
1 transmit interface
1 receive interface

ADC
Single ADC controller instantiated in the sensor subsystem
19 single-ended inputs
12-bit resolution

Analog comparators
19 analog comparators:
6 high-performance
13 low-power

DMA
8 unidirectional channels

Security
8k OTP
JTAG lock
On-die NVM read/write access control

Package type
10x10 mm, 144-BGA pkg

Crystal oscillators
32 MHz
32.768 KHz

Silicon oscillator
32 MHz
32.768 KHz

CPU clock generator
4/8/16/32 MHz
Low-power compute mode w/RTC
clock source

SoC states
Active, Sleep, and Off
Host processor states: C0–C2
Sensor subsystem states:
Sensing Active, Sensing Wait, and Sensing Standby

Platform power
DC-DC 1.8 V, 3.3 V

Operating temperature
-40 °C to +85 °C